unisonic technologies co., ltd cd4541 cmos ic www.unisonic.com.tw 1 of 7 copyright ? 2015 unisonic technologies co., ltd qw-r502-037.d programmable timer ? description the cd4541 programmable timer comprise a 16-stage binary counter, an integrated oscill ator for use with an external capacitor and two resistors, out put control logic, and a special power-on reset circuit. the counter divides the oscillator frequency by any of 4 digitally controlled division ratios. ? features * operates at 2 n frequency divider or as single transition timer * increments on positive edge clock transitions * wide supply voltage range: 3.0v ~ 15v * built-in low power rc oscillator * oscillator frequency range ~ dc to 100 khz * external clock applied to pin 3 can be used instead of * oscillator * available division ratios 2 8 , 2 10 , 2 13 , or 2 16 * high noise immunity: 0.45 v dd (typ) * master reset totally independ ent of automatic reset operation * automatic reset initializes all counters when power turns on * q/q select provides output logic level flexibility * high output drive min. one ttl load * maximum input leakage 1 a at 15v over full temperature * range ? ordering information ordering number lead free halogen free package packing CD4541-D14-T cd4541l-d14-t dip-14 tube - cd4541l-s14-r sop-14 tape reel - cd4541l-p14-t tssop-14 tube ? marking dip-14 sop-14 / tssop-14
cd4541 cmos ic unisonic technologies co., ltd 2 of 7 www.unisonic.com.tw qw-r502-037.d ? pin configuration mr n. c . ar r s a v dd b r tc mode q/q select q v ss 1 2 3 4 5 6 78 14 13 12 11 10 9 c tc n.c. ? truth table state pin 0 1 5 auto reset operatin g auto reset disabled 6 timer operational master reset on 9 output initially low after reset output initially high after reset 10 single cycle mode recycle mode ? division ratio table a b number of counter stages n count 2 n 0 0 13 8192 0 1 10 1024 1 0 8 256 1 1 16 65536 ? block diagram
cd4541 cmos ic unisonic technologies co., ltd 3 of 7 www.unisonic.com.tw qw-r502-037.d ? absolute maximum rating parameter symbol ratings unit supply voltage v dd -0.5 ~ +18 v input voltage v in -0.5 ~ v dd +0.5 v dip-14 700 power dissipation sop-14/ tssop-14 p d 500 mw junction temperature t j 125 c operating temperature t opr -20 ~ +85 c storage temperature t stg -40 ~ +150 c note: absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functiona l device operation is not implied. ? recommended operating conditions parameter symbol ratings unit supply voltage v dd 3 ~ 15 v input voltage v in 0 ~ v dd v operating temperature t opr -40 ~ +85 c ? dc electrical characteristics (t a =25c, unless otherwise specified.) parameter symbol test conditions min typ max unit v dd = 5v, v in =v dd or v ss 0.005 20 v dd =10v, v in =v dd or v ss 0.010 40 quiescent device current i dd v dd =15v, v in =v dd or v ss 0.015 80 a v dd =5v 0 0.05 v dd =10v, i i o i<1 a 0 0.05 low level output voltage v ol v dd =15v 0 0.05 v v dd =5v 4.95 5 v dd =10v, i i o i<1 a 9.95 10 high level output voltage v oh v dd =15v 14.95 15 v v dd =5v, v o =0.5v or 4.5v 2 1.5 v dd =10v, v o =1.0v or 9.0v 4 3.0 low level input voltage v il v dd =15v, v o =1.5v or 13.5v 6 4.0 v v dd =5v, v o =0.5v or 4.5v 3.5 3 v dd =10v, v o =1.0v or 9.0v 7.0 6 high level input voltage v ih v dd =15v, v o =1.5v or 13.5v 11.0 9 v v dd =5v, v o =0.4v 1.96 3.6 v dd =10v, v o =0.5v 2.66 9.0 low level output current (note) i ol v dd =15v, v o =1.5v 10.4 34.0 ma v dd =5v, v o =2.5v 4.27 130 v dd =10v, v o =9.5v 2.25 8.0 high level output current (note) i oh v dd =15v, v o =13.5v 8.8 30.0 ma v dd =15v, v in =0v -10 -5 -0.3 input current i in v dd =15v, v in =15v 10 -5 0.3 a note: i oh and i ol are tested one output at a time.
cd4541 cmos ic unisonic technologies co., ltd 4 of 7 www.unisonic.com.tw qw-r502-037.d ? ac electrical characteristics (note 1, t a =25 , c l =50pf (refer to test circuits)) parameter symbol test conditions min typ max unit v dd =5v 50 200 v dd =10v 30 100 output rise time t tlh v dd =15v 25 80 ns v dd =5v 50 200 v dd =10v 30 100 output fall time t thl v dd =15v 25 80 ns v dd =5v 1.8 4.0 v dd =10v 0.6 1.5 turn-off, turn-on propagation delay, clock to q (2 8 output) t plh , t phl v dd =15v 0.4 1.0 s v dd =5v 3.2 8.0 v dd =10v 1.5 3.0 turn-on, turn-off propagation delay, clock to q (2 16 output) t phl , t plh v dd =15v 1.0 2.0 s v dd =5v 400 200 v dd =10v 200 100 clock pulse width t wh(cl) v dd =15v 150 70 ns v dd =5v 2.5 1.0 v dd =10v 6.0 3.0 clock pulse frequency f cl v dd =15v 8.5 4.0 mhz v dd =5v 400 170 v dd =10v 200 75 mr pulse width t wh(r) v dd =15v 150 50 ns average input capacitance c i any input 5.0 7.5 pf power dissipation capacitance c pd (note 2) 100 pf notes: 1. ac parameters are guar anteed by dc correlated testing. 2. c pd determines the no load ac power c onsumption of any cmos device.
cd4541 cmos ic unisonic technologies co., ltd 5 of 7 www.unisonic.com.tw qw-r502-037.d ? operating characteristics with auto reset pin set to a ?0? the counter circuit is in itialized by turning on power. or with power already on, the counter circuit is reset when the master reset pin is set to a ?1?. both types of reset will result in synchronously resetting all counter stages in dependent of counter state. the rc oscillator frequency is determined by the external rc network, i.e.: and rs ~ 2 r tc where rs R 10 k ? the time select inputs (a and b) provide a two-bit address to output any one of four counter stages (2 8 , 2 10 , 2 13 , and 2 16 ). the 2 n counts as shown in the division ratio table repr esent the q output of the nth stage of the counter. when a is ?1?, 2 16 is selected for both states of b. however, when b is ?0?, normal counting is interrupted a nd the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputting 2 8 ). the q/q select output control pin provi des for a choice of output level. when the counter is in a reset condition and q/q select pin is set to a ?0? the q output is a ?0?. co rrespondingly, when q/q select pin is set to a ?1? the q output is a ?1?. when the mode control pin is set to a ?1?, the selected count is continually transmitted to the output. but, with mode pin ?0? and after a reset condition the rs flip-flo p resets (see logic diagram), counting commences and after 2 n-1 counts the rs flip-flop sets which causes the output to change state. hence, after another 2 n-1 counts the output will not change. thus, a master reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation. internal reset r tc 21 r s to clock circuit oscillator circuit using rc configuration 3 c tc
cd4541 cmos ic unisonic technologies co., ltd 6 of 7 www.unisonic.com.tw qw-r502-037.d ? test circuit and waveforms t plh t wh (c l ) 20 ns 20 ns 90% 50% 10% rs 50% t phl 50% t thl t tlh 90% 50% 10% q switching time test circuit and waveforms pulse generator rs ar q/q select mode a b mr q c l v ss v dd
cd4541 cmos ic unisonic technologies co., ltd 7 of 7 www.unisonic.com.tw qw-r502-037.d utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
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